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CS53L21
Low Power, Stereo Analog to Digital Converter
FEATURES
98 dB Dynamic Range (A-wtd) -88 dB THD+N Analog Gain Controls - +32 dB or +16 dB MIC Pre-Amplifiers - Analog Programmable Gain Amplifier (PGA)
SYSTEM FEATURES
24-bit Conversion 4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation - Stereo Record (ADC): 8.72 mW @ 1.8 V - Stereo Record (MIC to PGA and ADC): 13.73 mW @ 1.8 V
+20 dB Digital Boost Programmable Automatic Level Control (ALC) - Noise Gate for Noise Suppression - Programmable Threshold and Attack/Release Rates
Variable Power Supplies - 1.8 V to 2.5 V Digital & Analog - 1.8 V to 3.3 V Interface Logic
Independent Left/Right Channel Control Digital Volume Control High-Pass Filter Disable for DC Measurements Stereo 3:1 Analog Input MUX Dual MIC Inputs - Programmable, Low Noise MIC Bias Levels - Differential MIC Mix for Common Mode Noise Rejection
Power Down Management - ADC, MIC Pre-Amplifier, PGA Software Mode (IC(R) & SPITM Control) Hardware Mode (Stand-Alone Control) Flexible Clocking Options - Master or Slave Operation Digital Routing Mixes - Mono Mixes
Very Low 64 Fs Oversampling Clock Reduces Power Consumption
1.8 V to 3.3 V
1.8 V to 2.5 V
PCM Serial Interface
Hardware Mode or I2C & SPI Software Mode Control Data Level Translator
Digital Signal Processing Engine
ALC
Multibit Oversampling ADC Multibit Oversampling ADC
MUX
PGA MUX
+32 dB
Stereo Input 1 Stereo Input 2 Stereo Input 3 / Mic Input 1 & 2
Reset
Volume Controls High Pass Filters
Register Configuration
MUX
PGA
+32 dB
Serial Audio Output
ALC
MIC Bias
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
MAY `06 DS700PP1
CS53L21
APPLICATIONS
Portable Audio Players Digital Microphones Digital Voice Recorders Voice Recognition Systems Audio/Video Capture Cards
GENERAL DESCRIPTION
The CS53L21 is a highly integrated, 24-bit, 96 kHz, low power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system applications. The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone-level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. The Signal Processing Engine (SPE) controls left/right channel volume mixing, channel swap and channel mute functions. All volume-level changes may be configured to occur on soft ramp and zero cross transitions. The CS53L21 is available in a 32-pin QFN package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB53L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 63 for complete details. In addition to its many features, the CS53L21 operates from a low-voltage analog and digital core, making this A/D ideal for portable systems that require extremely low power consumption in a minimal amount of space.
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CS53L21
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .................................................................... 12 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................................... 13 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14 SWITCHING SPECIFICATIONS - IC CONTROL PORT ..................................................................... 16 SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 18 POWER CONSUMPTION .................................................................................................................... 19 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.1.1 Architecture ........................................................................................................................... 20 4.1.2 Line & MIC Inputs .................................................................................................................. 20 4.1.3 Signal Processing Engine ..................................................................................................... 20 4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20 4.1.5 Power Management .............................................................................................................. 20 4.2 Hardware Mode .............................................................................................................................. 21 4.3 Analog Inputs ................................................................................................................................. 22 4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 22 4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23 4.3.3 Digital Routing ....................................................................................................................... 23 4.3.4 Differential Inputs .................................................................................................................. 23 4.3.4.1 External Passive Components ................................................................................... 23 4.3.5 Analog Input Multiplexer ........................................................................................................ 25 4.3.6 MIC & PGA Gain ................................................................................................................... 25 4.3.7 Automatic Level Control (ALC) .............................................................................................. 26 4.3.8 Noise Gate ............................................................................................................................ 27 4.4 Signal Processing Engine ............................................................................................................... 28 4.4.1 Volume Controls .................................................................................................................... 28 4.4.2 Mono Channel Mixer ............................................................................................................. 28 4.5 Serial Port Clocking ........................................................................................................................ 29 4.5.1 Slave ..................................................................................................................................... 30 4.5.2 Master ................................................................................................................................... 30 4.5.3 High-Impedance Digital Output ............................................................................................. 31 4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 31 4.6 Digital Interface Formats ................................................................................................................ 31 4.7 Initialization ..................................................................................................................................... 32 4.8 Recommended Power-Up Sequence ............................................................................................. 32 4.9 Recommended Power-Down Sequence ........................................................................................ 33 4.10 Software Mode ............................................................................................................................. 34 4.10.1 SPI Control .......................................................................................................................... 34 4.10.2 IC Control ........................................................................................................................... 34 4.10.3 Memory Address Pointer (MAP) .......................................................................................... 36 4.10.3.1 Map Increment (INCR) ............................................................................................. 36 5. REGISTER QUICK REFERENCE ........................................................................................................ 37 6. REGISTER DESCRIPTION .................................................................................................................. 40 DS700PP1 3
CS53L21
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41 6.4 Interface Control (Address 04h) ..................................................................................................... 43 6.5 MIC Control (Address 05h) ............................................................................................................. 44 6.6 ADC Control (Address 06h) ............................................................................................................ 45 6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 47 6.8 SPE Control (Address 09h) ............................................................................................................ 48 6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ................. 49 6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 50 6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 51 6.12 Channel Mixer (Address 18h) ....................................................................................................... 51 6.13 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 52 6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 52 6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 53 6.16 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 54 6.17 Status (Address 20h) (Read Only) ............................................................................................... 55 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 56 7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS .......................................................................................................... 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 64
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15 Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15 Figure 5.Control Port Timing - IC ............................................................................................................. 16 Figure 6.Control Port Timing - SPI Format ................................................................................................ 17 Figure 7.Analog Input Architecture ............................................................................................................ 22 Figure 8.MIC Input Mix w/Common Mode Rejection ................................................................................. 24 Figure 9.Differential Input .......................................................................................................................... 24 Figure 10.ALC ........................................................................................................................................... 26 Figure 11.Noise Gate Attenuation ............................................................................................................. 27 Figure 12.Signal Processing Engine ......................................................................................................... 28 Figure 13.Master Mode Timing ................................................................................................................. 30 Figure 14.Tri-State Serial Port .................................................................................................................. 31 Figure 15.IS Format ................................................................................................................................. 31 Figure 16.Left-Justified Format ................................................................................................................. 32 Figure 17.Initialization Flow Chart ............................................................................................................. 33 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 19.Control Port Timing, IC Write ................................................................................................... 35 Figure 20.Control Port Timing, IC Read ................................................................................................... 35 4 DS700PP1
CS53L21
Figure 21.AIN & PGA Selection ................................................................................................................ 47 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56 Figure 23.ADC Passband Ripple .............................................................................................................. 60 Figure 24.ADC Stopband Rejection .......................................................................................................... 60 Figure 25.ADC Transition Band ................................................................................................................ 60 Figure 26.ADC Transition Band Detail ...................................................................................................... 60
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 21 Table 3. MCLK/LRCK Ratios .................................................................................................................... 30
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CS53L21 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
SDOUT (M/S)
DGND
MCLK
TSTN
SCLK
VD
32
31
30
29
28
27
VL
26
LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (IS/LJ) AD0/CS (TSTN) VA_PULLUP TSTO AGND TSTO
RESET
25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
AIN1B AIN1A AFILTB AFILTA AIN2B/BIAS AIN2A MICIN2/BIAS/AIN3B MICIN1/AIN3A
CS53L21
21 20 19 18 17
AGND
TSTO
Pin Name
LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (IS/LJ)
#
1
Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port.
2
3
Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface formats for the ADC. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip-select signal for SPI format. Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to DGND for normal operation. Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA using a 47 k resistor. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Analog Ground (Input) - Ground reference for the internal analog section. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin).
AD0/CS (TSTN)
4
VA_PULLUP TSTO AGND TSTO
5 6 7 8
6
TSTO
FILT+
NIC
NIC
VA
VQ
DS700PP1
CS53L21
TSTO NIC NIC VA AGND TSTO VQ FILT+ MICIN1/ AIN3A MICIN2/ BIAS/AIN3B AIN2A AIN2B/BIAS AFILTA AFILTB AIN1A AIN1B RESET VL VD DGND SDOUT (M/S) MCLK SCLK TSTN Thermal Pad 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). .Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left "floating". No other external connection should be made to this pin. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Filter Connection (Output) - Filter connection for the ADC inputs. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) -- Serial clock for the serial audio interface. Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal operation. Thermal relief pad for optimized heat dissipation. See "QFN Thermal Pad" on page 59.
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CS53L21
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW)
RESET SCL/CCLK (IS/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK SDOUT (M/S)
I/O
Input Input Input/Output Input Input Input/Output Input/Output Input/Output
Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS
Table 1. I/O Power Rails
Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V
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CS53L21 2. TYPICAL CONNECTION DIAGRAMS
+1.8 V or +2.5 V
1 F 0.1 F
See Note 4
0.1 F 47 k
+1.8 V or +2.5 V
1 F
Note 4: Series resistance in the path of the power supplies must be avoided.
VD
VA
VA_ PULLUP
CS53L21
AIN1A TSTN
1800 pF 1800 pF
* *
1 F
100
Left Analog Input 1
100 k 100 k
MCLK SCLK LRCK Digital Audio Processor SDOUT RESET SCL/CCLK SDA/CDIN AD0/CS
AIN1B
1 F
100
Right Analog Input 1 Left Analog Input 2
100 k 100 k
AIN2A
1800 pF 1800 pF
* 1 F *
1 F
100
AIN2B BIAS1 MICIN1 AIN3A BIAS2 AIN3B/MICIN2
100
Right Analog Input 2
Microphone Input
1 F 100 k
Microphone Bias
0.1 F
RL
See Note 3
2k
2k
+1.8 V, +2.5 V or +3.3 V
See Note 1 0.1 F
Note 3: The value of R L is dictated by the microphone cartridge.
VL
FILT+
Note 1: Resistors are required for IC control port operation
AGND
* *
150 pF 150 pF
10 F
AFILTA AFILTB VQ DGND
1 F
* Capacitors must be C0G or equivalent
Figure 1. Typical Connection Diagram (Software Mode)
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CS53L21
+1.8V or +2.5V
1 F 0.1 F
See Note 4
0.1 F 47 k
+1.8V or +2.5V
VD
VA
VA_ PULLUP
Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided.
CS53L21
TSTN
MCLK SCLK LRCK
VL or DGND (1)
AIN1A SDOUT/ M/S RESET IS/LJ MCLKDIV2 FILT+
1800 pF * 1 F 100 1800 pF * 100 1 F
Left Analog Input 1
100 k 100 k
Digital Audio Processor
AIN1B
Right Analog Input 1
AGND
* * 150 pF 150 pF
10 F
+1.8V, 2.5 V or +3.3V
VL
0.1 F
AFILTA AFILTB VQ DGND
1 F
* Capacitors must be C0G or equivalent
(1) Pull-up to VL (47 k Master Mode. for Pull-down to DGND for Slave Mode.
Figure 2. Typical Connection Diagram (Hardware Mode)
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DS700PP1
CS53L21 3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.) Parameters
DC Power Supply (Note 1) Analog Core Digital Core Serial/Control Port Interface Ambient Temperature Commercial - CNZ Automotive - DNZ VA VD VL TA 1.65 2.37 1.65 2.37 1.65 2.37 3.14 -10 -40 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85 V V V V V V V C C
Symbol
Min
Nom
Max
Units
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply Analog Digital Serial/Control Port Interface (Note 2) (Note 3)
Symbol
VA VD VL Iin
Min
-0.3 -0.3 -0.3 AGND-0.7 -0.3 -50 -65
Max
3.0 3.0 4.0 10 VA+0.7 VL+ 0.4 +115 +150
Units
V V V mA
Input Current Analog Input Voltage Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature
VIN
VIND TA Tstg
V
V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
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CS53L21 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max
A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 93 90 99 96 -86 -76 -36 -80 -
Parameter (Note 4)
VA = 1.8 V (nominal) Min Typ Max
90 87 96 93 -84 -73 -33 -78 -
Unit
dB dB dB dB dB
Analog In to ADC (PGA bypassed)
Dynamic Range Total Harmonic Distortion + Noise
Analog In to PGA to ADC Dynamic Range
PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -81 -79 -86 -32 -83 -80 -77 dB dB dB A-weighted unweighted A-weighted unweighted 92 89 85 82 98 95 91 88 89 86 82 79 95 92 88 85 dB dB dB dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB
Other Characteristics
DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation Full-scale Input Voltage ADC 0.74*VA PGA (0 dB) 0.75*VA MIC (+16 dB) MIC (+32 dB) ADC PGA MIC 90 0.78*VA 0.82*VA 0.794*VA 0.83*VA 0.129*VA 0.022*VA 20 39 50 0.74*VA 0.75*VA 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 20 39 50 0.82*VA 0.83*VA dB Vpp Vpp Vpp Vpp k k k SDOUT Code with HPF On 0.2 100 352 0.2 100 352 dB ppm/C LSB
Input Impedance (Note 5)
-
-
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CS53L21 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
Parameter (Note 4)
VA = 2.5 V (nominal) Min Typ Max
A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 91 78 99 96 -86 -76 -36 -78 -
VA = 1.8 V (nominal) Min Typ Max
88 85 96 93 -84 -73 -33 -76 -
Unit
dB dB dB dB dB
Analog In to ADC
Dynamic Range Total Harmonic Distortion + Noise
Analog In to PGA to ADC Dynamic Range
PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -80 -77 -86 -32 -83 -78 -75 dB dB dB A-weighted unweighted A-weighted unweighted 90 87 83 80 98 95 91 88 87 84 80 77 95 92 88 85 dB dB dB dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB
Other Characteristics
DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation Full-scale Input Voltage 0.74*VA ADC PGA (0 dB) 0.75*VA MIC (+16 dB) MIC (+32 dB) 18 ADC 40 PGA 50 MIC 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 0.82*VA 0.83*VA 0.74*VA 0.75*VA 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 0.82*VA 0.83*VA dB Vpp Vpp Vpp Vpp k k k SDOUT Code with HPF On 0.1 100 352 0.1 100 352 dB ppm/C LSB
Input Impedance (Note 5)
-
18 40 50
-
4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 5. Measured between AINxx and AGND. DS700PP1 13
CS53L21 ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 6)
Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner
Min
0 -0.09 0.6 33 -
Typ
7.6/Fs 3.7 24.2 10 10 /Fs
5
Max
0.4948 0.17 0.17 0
Unit
Fs dB Fs dB s Hz Hz Deg dB s
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz -
6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
Parameters RESET pin Low Pulse Width
MCLK Frequency MCLK Duty Cycle (Note 8) (Note 7)
Symbol
Min
1 1.024 45
Max
38.4 55
Units
ms MHz %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) td(MSB) ts(SDO-SK) th(SK-SDO) 4 8 4 50 45 45 40 20 30 12.5 25 50 100 55 64*Fs 55 52 kHz kHz kHz kHz % Hz % ns ns ns ns
LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge
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CS53L21
Parameters Master Mode (Note 9)
Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge td(MSB) ts(SDO-SK) th(SK-SDO) 1/tP All Speed Modes (Note 10) Fs 45 45 20 30 MCLK ---------------128 55 64*Fs 55 52 Hz % Hz % ns ns ns
Symbol
Min
Max
Units
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are settled. 8. See "Example System Clock Frequencies" on page 57 for typical MCLK frequencies. 9. See"Master" on page 30. 10. "MCLK" refers to the external master clock applied.
LRCK
ts(LK-SK)
// // // // td(MSB) th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 tP
SCLK
SDOUT
Figure 3. Serial Audio Interface Slave Mode Timing
LRCK SCLK
td(MSB)
// // // // th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 tP
SDOUT
Figure 4. Serial Audio Interface Master Mode Timing
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CS53L21 SWITCHING SPECIFICATIONS - IC CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter
SCL Clock Frequency
Symbol
fscl tirs tbuf thdst tlow thigh tsust (Note 11) thdd tsud trc tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 3450
Unit
kHz ns s s s s s s ns s ns s ns
RESET Rising Edge to Start
Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 5. Control Port Timing - IC
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CS53L21 SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter
CCLK Clock Frequency
Symbol
fsck tsrs tcss tcsh tscl tsch tdsu (Note 12) (Note 13) (Note 13) tdh tr2 tf2
Min
0 20 20 1.0 66 66 40 15 -
Max
6.0 100 100
Units
MHz ns ns s ns ns ns ns ns ns
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For fsck <1 MHz.
RST
tsrs
CS
tcss tsch tscl tr2 tcsh
CCLK
tf2 tdsu tdh
CDIN
Figure 6. Control Port Timing - SPI Format
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CS53L21 DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.) Parameters VQ Characteristics
Nominal Voltage Output Impedance DC Current Source/Sink (Note 14) FILT+ MICBIAS_LVL[1:0] = 00 MICBIAS_LVL[1:0] = 01 MICBIAS_LVL[1:0] = 10 MICBIAS_LVL[1:0] = 11 1 kHz 1 kHz 1 kHz 0.5*VA 23 VA 0.8*VA 0.7*VA 0.6*VA 0.5*VA 50 60 10 1 30 V k A V V V V V mA dB mW dB
Min
Typ
Max
Units
MIC BIAS Characteristics
Nominal Voltage
DC Current Source Power Supply Rejection Ratio (PSRR) Power Consumption (Normal Operation Worse Case) Power Supply Rejection Ratio (PSRR) (Note 15)
14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 16)
Input Leakage Current Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) Low-Level Output Voltage (IOL = 100 A) High-Level Input Voltage Low-Level Input Voltage VOH VOL VIH VIL VL - 0.2 0.68*VL 0.2 0.32*VL V V V V
Symbol
Iin
Min
-
Max
10 10
Units
A pF
16. See "Digital I/O Pin Characteristics" on page 8 for serial and control port power rails.
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CS53L21 POWER CONSUMPTION
See (Note 17) Power Ctl. Registers 02h 03h
Operation Reserved bit 6 Reserved bit 5 PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN PDN_MICB PDN_MICA PDN_MICBIAS
Typical Current (mA)
iVA
iVD
iVL (Note 20)
V
0 0 0.01 0.01 1.85 2.07 2.35 2.58 3.67 3.95 3.27 3.52 2.69 2.93 3.65 3.91 5.48 5.76 0 0 0.02 0.03 2.03 3.05 2.03 3.08 2.05 3.09 2.03 3.08 2.12 3.18 2.12 3.17 2.11 3.17 0 0 0 0 0.03 0.05 0.03 0.05 0.03 0.05 0.03 0.05 0.03 0.04 0.03 0.04 0.03 0.04
Total Power (mWrms)
0 0 0.05 0.10 7.05 12.94 7.95 14.29 10.36 17.71 9.61 16.62 8.72 15.40 10.45 17.84 13.73 22.45
1 2 3
Off (Note 18) Standby (Note 19) Mono Record
x x x x x x x x x x 1.8 2.5 x x x x x x 1 x x x 1.8 2.5 ADC 1 1 1 1 1 0 0 1 1 1 1.8 2.5 PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8 2.5 MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 0 1.8 (with Bias) 2.5 MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 1 1.8 (no Bias) 2.5
4
Stereo Record
ADC 1 1 1 1 0 0 0 1 1 1 1.8 2.5 PGA to ADC 1 1 0 0 0 0 0 1 1 1 1.8 2.5 MIC to PGA to ADC 1 1 0 0 0 0 0 0 0 1 1.8 (no Bias) 2.5
17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation. 18. RESET pin 25 held LO, all clocks and data lines are held LO. 19. RESET pin 25 held HI, all clocks and data lines are held HI. 20. VL current will slightly increase in master mode.
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CS53L21 4. APPLICATIONS
4.1 4.1.1 Overview Architecture
The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2
Line & MIC Inputs
The analog input portion of the A/D allows selection from and configuration of multiple combinations of stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC input with common mode rejection), two MIC bias outputs and independent channel control (including a high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume controls, including gain, boost, attenuation and inversion are also available.
4.1.3
Signal Processing Engine
The ADC data has independent volume controls and mixing functions such as mono mixes and left/right channel swaps.
4.1.4
Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire IC or three-wire SPI control port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
4.1.5
Power Management
Two Software Mode control registers provide independent power-down control of the ADC, PGA, MIC preamp and MIC bias, allowing operation in select applications with minimal power consumption.
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4.2 Hardware Mode
A limited feature-set is available when the A/D powers up in Hardware Mode (see "Recommended PowerUp Sequence" on page 32) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available. Hardware Mode Feature/Function Summary Feature/Function Default Configuration Stand-Alone Control
Power Control Device PGAx ADCx MIC Bias MICx Pre-Amplifier Serial Port Slave Serial Port Master Powered Up Powered Up Powered Up Powered Down Powered Down Enabled Auto-Detect Speed Mode Single-Speed Mode (Selectable) (Selectable) ADC Digital Boost Soft Ramp Zero Cross Invert PGAx Attenuator ALC Noise Gate (Selectable) Disabled Disabled Disabled Disabled 0 dB 0 dB Disabled Disabled Enabled Continuous DC Subtraction AIN1A to PGAA AIN1B to PGAB Disabled Enabled Enabled Disabled ADC Data to SPE ADC ADCA = L; ADCB = R Table 2. Hardware Mode Feature Summary
Note
-
-
Auto-Detect Speed Mode MCLK Divide Serial Port Master / Slave Selection Interface Control ADC Volume & Gain
"MCLKDIV2" pin 2 "M/S" pin 29 "IS/LJ" pin 3
see Section
4.5 on page 29
see Section
4.5 on page 29
see Section
4.6 on page 31
-
-
ADCx High-Pass Filter ADCx High-Pass Filter Freeze Line/MIC Input Select ADC mix Volume and Gain Invert Soft Ramp Zero Cross MIX
-
-
Signal Processing Engine (SPE) Data Selection (SPE Enable) Channel Swap
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4.3 Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel.
ADCA_MUTE ADCA_DBOOST ADCA_ATT[7:0] 0/-96dB 1dB steps PDN_ADCA
PGAA_VOL[5:0] ADC_SNGVOL SOFTA ZCROSSA +12/-3dB 0.5dB steps
MUX
MUX
ADCA_HPF FREEZE ADCA_HPF ENABLE ALCA_SRDIS ALCA_ZCDIS ALC_ENA
+20dB Digital Boost
Attenuator
SOFTA
Multibit Oversampling ADC
INV_ADCA
PGA
PDN_PGAA
MUX
+16/ 32 dB
AIN1A AIN2A AIN3A/ MICIN1
MICA_BOOST PDN_MICA
AINA_MUX[1:0] MICBIAS_LVL[1:0]
PCM Serial Interface
DIGMIX
MICMIX
ALC_ARATE[5:0] ALC_RRATE[5:0] MAX[2:0] MIN[2:0] ALC_ENB ALCB_SRDIS ALCB_ZCDIS
ALC
Noise Gate
NG_ALL NG_EN THRESH[3:0] NGDELAY[1:0]
MICBIAS
PDN_MICBIAS
MICBIAS_SEL PGAB_VOL[5:0] ADC_SNGVOL SOFTB ZCROSSB +12/-3dB 0.5dB steps
ADCB_DBOOST
PDN_ADCB SOFTB
MUX
MUX
ADCB_HPF FREEZE ADCB_HPF ENABLE
+20dB Digital Boost
Attenuator
Multibit Oversampling ADC
INV_ADCB
PGA
PDN_PGAB
MUX
+16/ 32 dB
AIN1B AIN2B/MICBIAS AIN3B/ MICIN2/ MICBIAS
MICB_BOOST PDN_MICB
ADCB_MUTE ADCB_ATT[7:0] 0/-96dB 1dB steps TO SIGNAL PROCESSING ENGINE (SPE) FROM SIGNAL PROCESSING ENGINE (SPE)
AINB_MUX[1:0]
Figure 7. Analog Input Architecture
4.3.1
Digital Code, Offset & DC Measurement
The ADC output data is in two's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow bit to be set to a `1'. Given the two's complement format, low-level signals may cause the MSB of the serial data to periodically toggle between `1' and `0', possibly introducing noise into the system as the bit switches back and forth. To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note that this offset is not removed (refer to "Analog Characteristics (Commercial - CNZ)" on page 12 and/or "Analog Characteristics (Automotive - DNZ)" on page 13 for the specified offset level). The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel. DC levels are measured relative to VQ and will be decoded as positive two's complement binary numbers above VQ and negative two's complement binary numbers below VQ.
Software Controls: "Status (Address 20h) (Read Only)" on page 55, "ADC Control (Address 06h)" on page 45.
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4.3.2 High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is "frozen" during normal operation, the current value of the DC offset for the corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the A/D with the high-pass filter enabled and the DC offset not "frozen" until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Freezing the DC offset. The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits. If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using the ADCx_HPFEN bit.
Software Controls: "ADC Control (Address 06h)" on page 45.
4.3.3
Digital Routing
The digital output of the ADC may be internally routed to the Signal Processing Engine (SPE). ADC output volume may be controlled using the ADCMIX [6:0] bits, and channel swaps can be done using the ADCA[1:0] and ADCB[1:0] bits. This "processed" ADC data can be selected for output in place of the ADC output data using the DIGMIX bit.
Software Controls: "ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)" on page 51, "Interface Control (Address 04h)" on page 43.
4.3.4
Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides common mode rejection of noise in digitally intense PCB's where the microphone signal traverses long traces, or across long microphone cables as illustrated in Figure 8. Since the mixer provides a differential combination of the two signals, the potential input mix may exceed the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX volume control to re-adjust a small signal to desired levels. The analog inputs may also be used as a differential input pair as illustrated in Figure 9. The two channels are differentially combined when the MICMIX bit is enabled.
4.3.4.1
External Passive Components
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kW may be combined with an external capacitor of 1 mF to achieve the cutoff frequency defined by the equation, An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
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1 fc = ---------------------------------------------- = 3.18 Hz 2 ( 50 k ) ( 1 F )
The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.
Software Controls: "Interface Control (Address 04h)" on page 43, "MIC Control (Address 05h)" on page 44.
MICBIAS
20
//
+
MICIN1
17
//
+
MICIN2
18
Figure 8. MIC Input Mix w/Common Mode Rejection
2.5 V
2.15 V 1.25 V 0.35 V 2.15 V 1.25 V 0.35 V
VA AINxA
AINxB
Full-Scale Differential Input Level (MICMIX=1) = (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS
Figure 9. Differential Input
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4.3.5 Analog Input Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGA's may be powered down allowing the user to select from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up. Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the two input channels. The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between these paths, the input resistance to the A/D will change accordingly. Refer to the input resistance characteristics in the Characteristic and Specification Tables for the input resistance of each path.
Software Controls: "Power Control 1 (Address 02h)" on page 40, "MIC Control (Address 05h)" on page 44 "ADCx Input Select, Invert & Mute (Address 07h)" on page 47.
4.3.6
MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. The PGA must be powered up when using the MIC pre-amp. The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software Controls: "Power Control 1 (Address 02h)" on page 40, "ADCx Input Select, Invert & Mute (Address 07h)" on page 47, "ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)" on page 49, "MIC Control (Address 05h)" on page 44.
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4.3.7 Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first and the PGA gain is then increased at a programmable release rate and maintains the resulting level above the minimum threshold. Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds.
Software Controls: "ALC Enable & Attack Rate (Address 1Ch)" on page 52, "ALC Release Rate (Address 1Dh)" on page 52, "ALC Threshold (Address 1Eh)" on page 53, "ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)" on page 49.
Input MIN[2:0]
below full scale
MAX[2:0]
below full scale
ALC
PGA Gain and/or Attenuator
ADCx_ATT[7:0] and PGAx_VOL[4:0] volume controls should NOT be adjusted manually when ALCx is enabled.
Output (after ALC) MIN[2:0]
below full scale
MAX[2:0]
below full scale
RRATE[5:0]
ARATE[5:0]
Figure 10. ALC
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4.3.8 Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before the noise gate attacks the signal. Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale. Ramp-down time to the maximum setting is affected by the SOFTx bit. Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog inputs are configured for differential signals (see "Differential Inputs" on page 23"Differential Inputs" on page 23), enable the NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold.
Software Controls: "Noise Gate Configuration & Misc. (Address 1Fh)" on page 54, "ADC Control (Address 06h)" on page 45.
Output (dB)
=1 EN G
-52 dB
N
N
G
=0 EN
Maximum Attenuation*
-64 dB
-80 dB
-96 THRESH[2:0]
-40
Input (dB)
Figure 11. Noise Gate Attenuation
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4.4 Signal Processing Engine
The SPE provides various signal processing functions that apply to the ADC data.
Software Controls: "SPE Control (Address 09h)" on page 48
INPUTS FROM ADCA and ADCB
SIGNAL PROCESSING ENGINE (SPE)
MUTE_ADCMIXA MUTE_ADCMIXB ADCMIXA_VOL[6:0] ADCMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps
VOL
Channel Swap
ADCA[1:0] ADCB[1:0]
Digital Mix to ADC Serial Interface
Figure 12. Signal Processing Engine
4.4.1
Volume Controls
The digital volume control functions offer independent control over the ADC signal path into the mixer. The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the SPE_SZC[1:0] bits.
Software Controls: "ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)" on page 51
4.4.2
Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for the ADC data. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap.
Software Controls: "Channel Mixer (Address 18h)" on page 51.
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4.5 Serial Port Clocking
The A/D serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode. Software Control:
"MIC Power Control & Speed Control (Address 03h)" on page 41, "SPE Control (Address 09h)" on page 48.
Pin Hardware Control:
"SDOUT, M/S" pin 29
Setting
47 k Pull-down 47 k Pull-up LO Slave Master
Selection
No Divide MCLK is divided by 2 prior to all internal circuitry.
"MCLKDIV2" pin 2
HI
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4.5.1 Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits. Auto-Detect
Disabled (Software Mode only) Enabled
QSM
512, 768, 1024, 1536, 2048, 3072
HSM
256, 384, 512, 768, 1024, 1536 512, 768, 1024*, 1536*
SSM
128, 192, 256, 384, 512, 768 256, 384, 512*, 768*
DSM
128, 192, 256, 384 128, 192, 256*, 384*
1024, 1536, 2048*, 3072* *MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
/ 128 / 128 / 256 / 512 /1 MCLK /2 1 /2 MCLKDIV2 /2 /4 /8
Double Speed Single Speed Half Speed Quarter Speed Double Speed Single Speed Half Speed Quarter Speed
00 01 10 11
LRCK Output (Equal to Fs)
0 SPEED[1:0]
00 01
SCLK Output
10 11
Figure 13. Master Mode Timing
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4.5.3 High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-impedance state, allowing another device to transmit serial port data without bus contention..
CS53L21
Transmitting Device #1
SDOUT
Transmitting Device #2
3ST_SP SCLK/LRCK
Receiving Device
Figure 14. Tri-State Serial Port
4.5.4
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow lower frequency sample rates.
4.6
Digital Interface Formats
The serial port operates in standard IS or Left-Justified digital interface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK. Figures 15-16 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 14 for exact timing relationship between clocks and data. Software Control: Hardware Control:
"Interface Control (Address 04h)" on page 43.
Pin
"IS/LJ" pin 3
Setting
LO HI Left-Justified Interface IS Interface
Selection
LRCK SCLK SDIN
MSB
L eft C h a n n e l
R ig ht C h a n n e l
LS B AOUTA / AINxA
M SB AOUTB / AINxB
LSB
MSB
Figure 15. IS Format
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LRCK SCLK SDIN
MSB AOUTA / AINxA LSB M SB AOUTB / AINxB LSB
L eft C h a n n e l
R ig ht C h a n n el
MSB
Figure 16. Left-Justified Format
4.7
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 33. The A/D enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, ADC and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in "Software Mode" on page 34. If a valid write sequence to the control port is not made within approximately 10 ms, the A/D will enter Hardware Mode. Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable. 2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode. 3. For Software Mode operation, set the PDN bit to `1'b in under 10 ms. This will place the device in "standby". 4. Load the desired register settings while keeping the PDN bit set to `1'b. 5. Start MCLK to the appropriate frequency, as discussed in Section 4.5. 6. Set the PDN bit to `0'b. 7. Apply LRCK and SCLK for normal operation to begin. 8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
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4.9 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the A/D in standby, 1. Mute the ADC's. 2. Set the PDN bit in the power control register to `1'b. The A/D will not power down until it reaches a fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. Bring RESET low.
No Power 1. No audio signal generated.
Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default.
PDN bit = '1'b?
Yes
Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings.
No No RESET = Low? Yes Valid MCLK Applied?
No 20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged.
No
Control Port Valid Write Seq. within 10 ms?
Yes
ADC Initialization 2048 internal MCLK cycle delay
Power Off Transition 1. Audible pops.
Hardware Mode Minimal feature set support.
Software Mode Registers setup to desired settings.
Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed.
Reset Transition 1. Pops suppressed.
No Valid MCLK/LRCK Ratio? Yes RESET = Low
ERROR: Power removed
Normal Operation Audio signal generated per control port or standalone settings.
PDN bit set to '1'b (software mode only)
Figure 17. Initialization Flow Chart
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CS53L21
4.10 Software Mode
The control port is used to access the registers allowing the A/D to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in two modes: SPI and IC, with the A/D acting as a slave device. Software Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit address state.
4.10.1 SPI Control
In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored. Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +n
6 1 0
CDIN
1
0
0
1
0
1
0
6
5
4
3
Figure 18. Control Port Timing in SPI Mode
4.10.2 IC Control
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS53L21 is being reset. The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto34 DS700PP1
CS53L21
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to the CS53L21 from the microcontroller after each transmitted byte.
24 25 26 27 28
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
SCL
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
0
1
AD0
6
5
4
3
ACK START
ACK
ACK
ACK STOP
Figure 19. Control Port Timing, IC Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
0 1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 20. Control Port Timing, IC Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto-increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100101x1 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
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CS53L21
4.10.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details.
4.10.3.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
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CS53L21 5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. "Reserved" registers must maintain their default state.
Addr
01h
Function
ID p 40 default
7
Chip_ID4 1 Reserved 0
6
Chip_ID3 1 Reserved
5
Chip_ID2 0 Reserved
4
Chip_ID1 1 PDN_PGAB 0
3
Chip_ID0 1 PDN_PGAA 0
2
Rev_ID2 0 PDN_ADCB 0
1
Rev_ID1 0 PDN_ADCA 0
0
Rev_ID0 1 PDN 0
02h
Power Ctl. 1 p 40 default
1(See Note 1(See Note 2 2 on page on page 40) 40) SPEED1 0 M/S 0 ADCB_ DBOOST 0 ADCB_HP FRZ 0 SPEED0 1 Reserved 0 ADCA_ DBOOST 0 ADCA_HPF EN 1
03h
Speed Ctl. & Power Ctl. 2 p 41 default
AUTO 1 Reserved 0 ADC_SNGVOL 0 ADCB_HPF EN 1 AINB_MUX1
3-ST_SP 0 Reserved 0 MICBIAS_ SEL 0 ADCA_HP FRZ 0
PDN_MICB 1 Reserved 0 MICBIAS_ LVL1 0 SOFTB 0 INV_ADCB
PDN_MICA 1 ADC_IS/LJ 0 MICBIAS_ LVL0 0 ZCROSSB 0 INV_ADCA
PDN_ MICBIAS 1 DIGMIX 0 MICB_ BOOST 0 SOFTA 0 ADCB_ MUTE 0 Reserved 0 SPE_SZC1 1 PGAA VOL1 0 PGAB VOL1 0 ADCA_ ATT1 0 ADCB_ ATT1
MCLKDIV2 0 MICMIX 0 MICA_ BOOST 0 ZCROSSA 0 ADCA_ MUTE 0 Reserved 0 SPE_SZC0 0 PGAA VOL0 0 PGAB VOL0 0 ADCA_ ATT0 0 ADCB_ ATT0
04h
Interface Ctl. p 43 default
05h
MIC Control & Misc. p 44 default
06h
ADC Control p 45 default
07h
ADC Input Select , Invert, Mute p 47 default
AINB_MUX AINA_MUX1 AINA_MUX0 0 0 Reserved 1 SPE_ ENABLE 0 ALCA_ZC DIS 0 ALCB_ZC DIS 0 ADCA_ ATT6 0 ADCB_ ATT6 0 Reserved 1 FREEZE 0 Reserved 0 Reserved 0 Reserved 0 PGAA VOL4 0 PGAB VOL4 0 ADCA_ ATT4 0 ADCB_ ATT4
0 Reserved 0
0 Reserved 0 Reserved 0 PGAA VOL3 0 PGAB VOL3 0 ADCA_ ATT3 0 ADCB_ ATT3
0 Reserved 0 Reserved 1 PGAA VOL2 0 PGAB VOL2 0 ADCA_ ATT2 0 ADCB_ ATT2
08h
Reserved default
09h
SPE Control p 48 default
Reserved 0 ALCA_SR DIS 0 ALCB_SR DIS 0 ADCA_ ATT7 0 ADCB_ ATT7
0Ah
ALCA SZC & PGAA Volume p 49 default
0 Reserved
0Bh
ALCB SZC & PGAB Volume p 49 default
0 ADCA_ ATT5 0 ADCB_ ATT5
0Ch ADCA Attenuator p 50 default 0Dh ADCB Attenuator
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CS53L21
Addr Function
p 50 default 0Eh Vol. Control ADCMIXA p 51 default 0Fh Vol. Control ADCMIXB p 51 default 10h Reserved default 11h Reserved default 12h Reserved default 13h Reserved default 14h Reserved default 15h Reserved default 16h Reserved default 17h Reserved default 18h ADC Channel Mixer p 51 default 19h Reserved default 1Ah Reserved Reserved 0 Reserved 0 default 1Ch ALC Enable & Attack Rate ALC_ENB 0 ALC_ENA 0 ALC_ARATE AALC_RATE ALC_ARATE ALC_ARATE ALC_ARATE ALC_ARATE 3 2 1 0 5 4 0 0 0 0 0 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 ADCA1 0 Reserved 0 ADCA0 0 Reserved 0 ADCB1 0 Reserved 0 ADCB0 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
7
0 MUTE_ADC MIXA 1 MUTE_ADC MIXB 1 Reserved 1
6
0 ADCMIXA VOL6 0 ADCMIXB VOL6 0 Reserved 0
5
0 ADCMIXA VOL5 0 ADCMIXB VOL5 0 Reserved 0
4
0 ADCMIXA VOL4 0 ADCMIXB VOL4 0 Reserved 0
3
0 ADCMIXA VOL3 0 ADCMIXB VOL3 0 Reserved 0
2
0 ADCMIXA VOL2 0 ADCMIXB VOL2 0 Reserved 0
1
0 ADCMIXA VOL1 0 ADCMIXB VOL1 0 Reserved 0
0
0 ADCMIXA VOL0 0 ADCMIXB VOL0 0 Reserved 0
default 1Bh Reserved
p 52
default
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Addr Function 7
Reserved 0 MAX2 0 NG_ALL 0 Reserved 0 Reserved 0 default
6
Reserved 0 MAX1 0 NG_EN 0 SP_CLK ERR 0 Reserved 1
5
4
3
2
1
0
1Dh ALC Release Rate p 52 default 1Eh ALC Threshold p 53 default 1Fh Noise Gate Config p 54 default 20h Status p 55 default 21h Reserved
ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE 5 4 3 2 1 0 1 MAX0 0 NG_BOOST 0 1 MIN2 0 THRESH2 0 1 MIN1 0 THRESH1 0 1 MIN0 0 THRESH0 0 1 Reserved 0 NGDELAY1 0 1 Reserved 0 NGDELAY0 0
SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL 0 Reserved 0 0 Reserved 1 0 Reserved 0 0 Reserved 0 0 Reserved 0 0 Reserved 0
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CS53L21 6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All "Reserved" registers must maintain their default state.
6.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
6 Chip_ID3 5 Chip_ID2 4 Chip_ID1 3 Chip_ID0 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0
7 Chip_ID4
Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS53L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2
Power Control 1 (Address 02h)
6 Reserved 5 Reserved 4 PDN_PGAB 3 PDN_PGAA 2 PDN_ADCB 1 PDN_ADCA 0 PDN
7 Reserved
Notes: 1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the A/D has fully powered up will mute the selected channel without achieving any power savings. 2. Reserved bits 5 and 6 should always be set "high" by the user to minimize power consumption during normal operation. Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit.
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Power Down PGA X (PDN_PGAX) Default: 0 0 - Disable 1 - Enable Function: PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control 1 (Address 02h) Note 1 above. This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to "ADCX Input Select Bits (AINX_MUX[1:0])" on page 47 for the required settings. Power Down ADC X (PDN_ADCX) Default: 0 0 - Disable 1 - Enable Function: ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page 40. Power Down (PDN) Default: 0 0 - Disable 1 - Enable Function: The entire A/D will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode.
6.3
MIC Power Control & Speed Control (Address 03h)
7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 PDN_MICB 2 PDN_MICA 1 PDN_MICBIAS 0 MCLKDIV2
Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the A/D when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 30. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
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CS53L21
Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the A/D in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above). Tri-State Serial Port Interface (3ST_SP) Default: 0 0 - Disable 1 - Enable Function: When enabled and the device is configured as a master, all serial port outputs (clocks and data) are placed in a high impedance state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a high-impedance state. The other signals will remain as inputs. Power Down MIC X (PDN_MICX) Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone pre-amplifier for channel x will be in a power-down state. Power Down MIC BIAS (PDN_MICBIAS) Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone bias circuit will be in a power-down state. MCLK Divide By 2 (MCLKDIV2) Default: 0 0 - Disabled 1 - Divide by 2 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode.
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6.4 Interface Control (Address 04h)
6 M/S 5 Reserved 4 Reserved 3 Reserved 2 ADC_IS/LJ 1 DIGMIX 0 MICMIX 7 Reserved
Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port.
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CS53L21
ADC IS or Left-Justified (ADC_IS/LJ) Default: 0 0 - Left-Justified 1 - IS Function: Selects either the IS or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in this section "Digital Interface Formats" on page 31. Digital Mix (DIGMIX) Default: 0 DIGMIX 0 1 Function: Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either "raw" ADC data or SPE processed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Microphone Mix (MICMIX) Default: 0 0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT. 1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT. Function: Selects between the ADC stereo mix or a differential mix of analog inputs A and B. SPE_ENABLE x 0 1 Mix Selected ADC data to ADC serial port, SDOUT data. Reserved SPE Processed ADC data to ADC serial port, SDOUT data.
6.5
MIC Control (Address 05h)
7 6 5 4 3 2 1 0
ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 MICB_BOOST MICA_BOOST
ADC_SNGVOL
ADC Single Volume Control (ADC_SNGVOL) Default: 0 0 - Disabled 1 - Enabled Function: The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL bit is enabled and the ALC_ENB control register is ignored.
44
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CS53L21
ADCx 20 dB Digital Boost (ADCx_DBOOST) Default: 0 0 - Disabled 1 - Enabled Function: Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path. MIC Bias Select (MICBIAS_SEL) Default: 0 0 - MICBIAS on AIN3B/MICIN2 pin 1 - MICBIAS on AIN2B pin Function: Determines the output pin for the internally generated MICBIAS signal. If set to `0'b, the MICBIAS is output on the AIN3B/MICIN2 pin. If set to `1'b, the MICBIAS is output on the AIN2B pin. MIC Bias Level (MICBIAS_LVL[1:0]) Default: 00 00 - 0.8 x VA 01 - 0.7 x VA 10 - 0.6 x VA 11 - 0.5 x VA Function: Determines the output voltage level of the MICBIAS output. MIC X Preamplifier Boost (MICX_BOOST) Default: 0 0 - +16 dB Gain 1 - +32 dB Gain Function: Determines the amount of gain applied to the microphone preamplifier for channel x.
6.6
ADC Control (Address 06h)
3 SOFTB 2 ZCROSSB 1 SOFTA 0 ZCROSSA
7 6 5 4 ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ
ADCX High-Pass Filter Enable (ADCX_HPFEN) Default: 1 0 - High-pass filter is disabled 1 - High-pass filter is enabled Function: When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to `0', the high-pass filter will be disabled. For DC measurements, this bit must be cleared to `0'. "ADC Digital Filter Characteristics" on page 14. DS700PP1 45
CS53L21
ADCX High-Pass Filter Freeze (ADCX_HPFRZ) Default: 0 0 - Continuous DC Subtraction 1 - Frozen DC Subtraction Function: The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to `1'. See "ADC Digital Filter Characteristics" on page 14. Soft Ramp CHX Control (SOFTX) Default: 0 0 - Disabled 1 - Enabled Function: Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital attenuation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period. PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods. Soft Ramp & Zero Cross Enabled When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing. Zero Cross CHX Control (ZCROSSX) Default: 0 0 - Disabled 1 - Enabled Function: Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp & Zero Cross Enabled When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing. The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit. SOFTx
0 0 1 1
ZCROSSx
0 1 0 1
Analog PGA Volume (PGAx_VOL[4:0])
Volume changes immediately. Volume changes at next zero cross time. Volume changes in 0.5 dB steps. Volume changes in 0.5 dB steps at every signal zero-cross.
Digital Attenuator (ADCx_ATT[7:0])
Volume changes immediately. Volume changes immediately. Change volume in 0.125 dB steps. Change volume in 0.125 dB steps.
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CS53L21
6.7 ADCx Input Select, Invert & Mute (Address 07h)
6 AINB_MUX0 5 AINA_MUX1 4 AINA_MUX0 3 INV_ADCB 2 INV_ADCA 1 0 ADCB_MUTE ADCA_MUTE 7 AINB_MUX1
ADCX Input Select Bits (AINX_MUX[1:0]) Default: 00 PDN_PGAx
0 0 0 0 1 1 1 1
AINx_MUX[1:0]
00 01 10 11 00 01 10 11
Selected Path to ADC
AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx AIN1x AIN2x AIN3x/MICINx Reserved
Function: Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when PDN_PGAx is disabled. See Figure 21.
AIN1x AIN2x AIN1x AIN2x AIN3x
MUX
ADC
MUX
+16/ 32 dB
PGA
AIN3x / MICINx
Decoder
AINx_MUX[1:0] PDN_PGAx
Figure 21. AIN & PGA Selection
ADCX Invert Signal Polarity (INV_ADCX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the ADC x channel. ADCX Channel Mute (ADCX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit (SOFT). DS700PP1 47
CS53L21
6.8 SPE Control (Address 09h)
6 SPE_ENABLE 5 FREEZE 4 Reserved 3 Reserved 2 Reserved 1 SPE_SZC1 0 SPE_SZC0 7 Reserved
SPE_ENABLE Default: 0 0 - Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
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SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.9
ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
5 Reserved 4 PGAX_VOL4 3 PGAX_VOL3 2 PGAX_VOL2 1 PGAX_VOL1 0 PGAX_VOL0
7 6 ALCX_SRDIS ALCX_ZCDIS
ALCX Soft Ramp Disable (ALCX_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.
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CS53L21
ALCX Zero Cross Disable (ALCX_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step. PGA X Gain Control (PGAX_VOL[4:0]) Default: 00000 Binary Code
11000 *** 01010 *** 00000 11111 11110 *** 11001 11010
Volume Setting
+12 dB *** +5 dB *** 0 dB -0.5 dB -1 dB *** -3 dB -3 dB
Function: The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft & Zero Cross bits (ALCX_SRDIS & ALCX_ZCDIS). Note: When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manually.
6.10
ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
6 ADCx_ATT6 5 ADCx_ATT5 4 ADCx_ATT4 3 ADCx_ATT3 2 ADCx_ATT2 1 ADCx_ATT1 0 ADCx_ATT0
7 ADCx_ATT7
ADCX Attenuation Control (ADCX_ATT[7:0]) Default: 00h Binary Code
0111 1111 *** 0000 0000 1111 1111 1111 1110 *** 1010 0000 *** 1000 0000
Volume Setting
0 dB *** 0 dB -1 dB -2 dB *** -96 dB *** -96 dB
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CS53L21
Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two's complement, as shown in the table above. Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually.
6.11
7
ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)
6 5 4 3 2 1 0
MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0
Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register. ADCX Mixer Channel Mute (MUTE_ADCMIXX) Default: 1 0 - Disabled 1 - Enabled Function: The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]). ADCX Mixer Volume Control (ADCMIXX_VOL[6:0]) Default = 000 0000 Binary Code
001 1000 *** 000 0000 111 1111 111 1110 *** 001 1001
Volume Setting
+12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -51.5 dB
Function: The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above.
6.12
Channel Mixer (Address 18h)
6 Reserved 5 Reserved 4 Reserved 3 ADCA1 2 ADCA0 1 ADCB1 0 ADCB0
7 Reserved
Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register. Channel Mixer (ADCx[1:0]) Default: 00 ADCA[1:0]
00
SDOUT
L
ADCB[1:0]
00
SDOUT
R
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ADCA[1:0]
01 10 11
SDOUT
L+R ----------2 R
ADCB[1:0]
01 10 11
SDOUT
L+R ----------2 L
Function: Implements mono mixes of the left and right channels as well as a left/right channel swap.
6.13
ALC Enable & Attack Rate (Address 1Ch)
6 ALC_ENA 5 4 3 2 1 0 ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
7 ALC_ENB
ALC Enable (ALC_ENX) Default: 0 0 - Disabled 1 - Enabled Function: Enables automatic level control for ADC channel x. Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually.
ALC Attack Rate (ARATE[5:0]) Default: 000000 Binary Code
000000 *** 111111
Attack Time
Fastest Attack *** Slowest Attack
Function: Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the ALC threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSSx bit settings unless the disable bit for each function is enabled.
6.14
ALC Release Rate (Address 1Dh)
6 Reserved 5 4 3 2 1 0 ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
7 Reserved
ALC Release Rate (RRATE[5:0]) Default: 111111 Binary Code
000000 *** 111111
Release Time
Fastest Release *** Slowest Release
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Function: Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting. The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled.
6.15
ALC Threshold (Address 1Eh)
6 MAX1 5 MAX0 4 MIN2 3 MIN1 2 MIN0 1 Reserved 0 Reserved
7 MAX2
Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB)
0 -3 -6 -9 -12 -18 -24 -30
000 001 010 011 100 101 110 111
Function: Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack rate. Minimum Threshold (MIN[2:0]) Default: 000 MIN[2:0]
000 001 010 011 100 101 110 111
Threshold Setting (dB)
0 -3 -6 -9 -12 -18 -24 -30
Function: Sets the minimum level at which to disengage the ALC's attenuation or amplify the input signal at a rate set in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the minimum setting. This provides a more natural sound as the ALC attacks and releases. DS700PP1 53
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6.16 Noise Gate Configuration & Misc. (Address 1Fh)
6 NG_EN 5 NG_BOOST 4 THRESH2 3 THRESH1 2 THRESH0 1 NGDELAY1 0 NGDELAY0 7 NG_ALL
Noise Gate Channel Gang (NG_ALL) Default: 0 0 - Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect. Noise Gate Enable (NG_EN) Default: 0 0 - Disabled 1 - Enabled Function: Enables the noise gate. Maximum attenuation is relative to all gain settings applied. Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0]) Default: 000 THRESH[2:0]
000 001 010 011 100 101 110 111
Minimum Setting (NG_BOOST = `0'b)
-64 dB -67 dB -70 dB -73 dB -76 dB -82 dB Reserved Reserved
Minimum Setting (NG_BOOST = `1'b)
-34 dB -37 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB
Function: Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST = `1'b adds 30 dB to the threshold settings. Noise Gate Delay Timing (NGDELAY[1:0]) Default: 00 00 - 50 ms 01 - 100 ms 10 - 150 ms 11 - 200 ms Function: Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled. 54 DS700PP1
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6.17 Status (Address 20h) (Read Only)
6 SP_CLKERR 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 ADCA_OVFL 0 ADCB_OVFL 7 Reserved
For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A "0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See "Serial Port Clocking" on page 29"Serial Port Clocking" on page 29 for valid clock ratios. Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
ADC Overflow (ADCX_OVFL) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the associated ADC's.
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CS53L21 7. ANALOG PERFORMANCE PLOTS
7.1 ADC_FILT+ Capacitor Effects on THD+N
The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB53L21 using an Audio Precision analyzer.
-60
-64
1 F 10 F 22 F Legend - Capacitor Value on ADC_FILT+
-68
-72
-76 d B F S
-80
-84
-88
-92
-96
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects
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CS53L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
Sample Rate LRCK (kHz)
8 11.025 12
1024x
8.1920 11.2896 12.2880
MCLK (MHz) 1536x 2048x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
3072x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
512x
8.1920 11.2896 12.2880
768x
12.2880 16.9344 18.4320
MCLK (MHz) 1024x*
16.3840 22.5792 24.5760
1536x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
384x
12.2880 16.9344 18.4320
MCLK (MHz) 512x*
16.3840 22.5792 24.5760
768x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
192x
MCLK (MHz) 256x*
16.3840 22.5792 24.5760
384x*
24.5760 33.8688 36.8640
12.2880 16.9344 18.4320
*The"MCLKDIV2" pin 4 must be set HI.
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8.2 Auto Detect Disabled
Sample Rate LRCK (kHz)
8 11.025 12
512x
6.1440
768x
6.1440 8.4672 9.2160
MCLK (MHz) 1024x 1536x
8.1920 11.2896 12.2880 12.2880 16.9344 18.4320
2048x
16.3840 22.5792 24.5760
3072x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
256x
6.1440
384x
6.1440 8.4672 9.2160
512x
8.1920 11.2896 12.2880
MCLK (MHz) 768x
12.2880 16.9344 18.4320
1024x
16.3840 22.5792 24.5760
1536x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
MCLK (MHz) 384x 512x
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
768x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
MCLK (MHz) 192x 256x
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
384x
24.5760 33.8688 36.8640
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CS53L21 9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-resolution converter, the CS53L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration.
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CS53L21 10.DIGITAL FILTERS
Figure 23. ADC Passband Ripple
Figure 24. ADC Stopband Rejection
Figure 25. ADC Transition Band
Figure 26. ADC Transition Band Detail
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CS53L21 11.PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS53L21 12.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
D b e Pin #1 Corner
Pin #1 Corner
E
E2
A1 A Top View Side View
L
D2
Bottom View
DIM
A A1 b D D2 E E2 e L
MIN
-0.0000 0.0071 0.1280 0.1280 0.0118
INCHES NOM
--0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157
MAX
0.0394 0.0020 0.0110 0.1319 0.1319 0.0197
MIN
-0.00 0.18 3.25 3.25 0.30
MILLIMETERS NOM
--0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40
NOTE MAX
1.00 0.05 0.28 3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1
JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board
Symbol
JA
Min
-
Typ
52 38
Max
-
Units
C/Watt
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CS53L21 13.ORDERING INFORMATION
Product
CS53L21
Description
Low-Power Stereo A/D CS53L21 Evaluation Board
Package Pb-Free
32L-QFN Yes
Grade
Temp Range
Container
Order #
Commercial -10 to +70 C Automotive CDB53L21 No -40 to +85 C -
Rail CS53L21-CNZ Tape & Reel CS53L21-CNZR Rail CS53L21-DNZ Tape & Reel CS53L21-DNZR CDB53L21
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
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CS53L21 15.REVISION HISTORY
Revision
A1 Initial Release Adjusted the minimum voltage specification in "Specified Operating Conditions" section on page 11. Adjusted maximum "Analog In to PGA to ADC" THD+N performance specification in "Analog Characteristics (Commercial - CNZ)" on page 12. Corrected Interchannel Gain Mismatch specification in "Analog Characteristics (Commercial - CNZ)" on page 12 and "Analog Characteristics (Automotive - DNZ)" on page 13. Adjusted ADC full scale input voltage specification in "Analog Characteristics (Commercial - CNZ)" on page 12 and "Analog Characteristics (Automotive - DNZ)" on page 13. Removed td timing specification from table in section "Switching Specifications - Serial Port" on page 14. Corrected Group Delay characteristic in table in section "ADC Digital Filter Characteristics" on page 14. Adjusted timing specifications td(MSB) from 40 ns to 52 ns and ts(SDO-SK) from 30 ns to 20 ns in table in section "Switching Specifications - Serial Port" on page 14. Adjusted IC timing specifications tack from 1000 ns to 3450 ns in table in section "" on page 15. Modified the Typ. Conn. HW and SW figures by adding a pull-up to the VA_HP pin and changed AFILTA, B cap values from 1000 pF to 150 pF. Modified the Pin Descriptions table description for pin 5 to add a pull-up. Adjusted High-Level Input Voltage specifications VIH from 0.65VL to 0.68VL and VIL from 0.35VL to 0.32VL in table in section "Digital Interface Specifications & Characteristics" on page 18. Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 7 on page 22. Modified ALC Recommended Settings in section "Automatic Level Control (ALC)" on page 26. Modified step 2 of the "Recommended Power-Down Sequence" on page 33. Corrected default values for ALC and Limiter Release Rates shown in "Register Quick Reference" on page 37. Corrected default value for the SPE_SZC bits in "SPE Control (Address 09h)" on page 48. Corrected ADC Filter Response shown in Figures 23, 24, 25, and 26 on page 60. Corrected ADC_SNGVOL description in "MIC Control (Address 05h)" on page 44.
Changes
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Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
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